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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1995 copyright ? intel corporation, 1995 order number: 290406-007 1-mbit (128k x 8) boot block flash memory 28f001bx-t/28f001bx-b/28f001bn-t/28f001bn-b y high-integration blocked architecture e one 8 kb boot block w/lock out e two 4 kb parameter blocks e one 112 kb main block y 100,000 erase/program cycles per block y simplified program and erase e automated algorithms via on-chip write state machine (wsm) y sram-compatible write interface y deep power-down mode e 0.05 m ai cc typical e 0.8 m ai pp typical y 12.0v g 5% v pp y high-performance read e 70/75 ns, 90 ns, 120 ns, 150 ns maximum access time e 5.0v g 10% v cc y hardware data protection feature e erase/write lockout during power transitions y advanced packaging, jedec pinouts e 32-pin pdip e 32-lead plcc, tsop y etox tm ii nonvolatile flash technology e eprom-compatible process base e high-volume manufacturing experience y extended temperature options intel's 28f001bx-b and 28f001bx-t combine the cost-effectiveness of intel standard flash memory with features that simplify write and allow block erase. these devices aid the system designer by combining the functions of several components into one, making boot block flash an innovative alternative to eprom and eeprom or battery-backed static ram. many new and existing designs can take advantage of the 28f001bx's integration of blocked architecture, automated electrical reprogramming, and standard processor interface. the 28f001bx-b and 28f001bx-t are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of 8 bits. they are offered in 32-pin plastic dip, 32-lead plcc and 32-lead tsop packages. pin assignment conform to jedec standards for byte-wide eproms. these devices use an integrated command port and state machine for simplified block erasure and byte reprogramming. the 28f001bx-t's block locations pro- vide compatibility with microprocessors and microcontrollers that boot from high memory, such as intel's mcs -186 family, 80286, i386 tm , i486 tm , i860 tm and 80960ca. with exactly the same memory segmentation, the 28f001bx-b memory map is tailored for microprocessors and microcontrollers that boot from low memory, such as intel's mcs-51, mcs-196, 80960kx and 80960sx families. all other features are identical, and unless otherwise noted, the term 28f001bx can refer to either device throughout the remainder of this document. the boot block section includes a reprogramming write lock out feature to guarantee data integrity. it is designed to contain secure code which will bring up the system minimally and download code to the other locations of the 28f001bx. intel's 28f001bx employs advanced cmos circuitry for systems requiring high- performance access speeds, low power consumption, and immunity to noise. its access time provides no-wait-state performance for a wide range of microprocessors and microcontrollers. a deep-powerdown mode lowers power consumption to 0.25 m w typical through v cc , crucial in laptop computer, handheld instru- mentation and other low-power applications. the rp y power control input also provides absolute data protec- tion during system powerup or power loss. manufactured on intel's etox process base, the 28f001bx builds on years of eprom experience to yield the highest levels of quality, reliability, and cost-effectiveness. note: the 28f001bn is equivalent to the 28f001bx.
28f001bx-t/28f001bx-b 290406 1 figure 1. 28f001bx block diagram table 1. pin description symbol type name and function a 0 a 16 input address inputs for memory addresses. addresses are internally latched during a write cycle. dq 0 dq 7 input/ data inputs/outputs: inputs data and commands during memory write cycles; outputs data during memory, status register and identifier read cycles. the output data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. data is internally latched during a write cycle. ce y input chip enable: activates the device's control logic, input buffers, decoders and sense amplifiers. ce y is active low; ce y high deselects the memory device and reduces power consumption to standby levels. rp y input powerdown: puts the device in deep powerdown mode. rp y is active low; rp y high gates normal operation. rp y e v hh allows programming of the boot block. rp y also locks out erase or write operations when active low, providing data protection during power transitions. rp y active resets internal automation. exit from deep powerdown sets device to read array mode. oe y input output enable: gates the device's outputs through the data buffers during a read cycle. oe y is active low. oe y e v hh (pulsed) allows programming of the boot block. we y input write enable: controls writes to the command register and array blocks. we y is active low. addresses and data are latched on the rising edge of the we y pulse. v pp erase/program power supply for erasing blocks of the array or programming bytes of each block. note: with v pp k v ppl max, memory contents cannot be altered. v cc device power supply: (5v g 10%) gnd ground 2
28f001bx-t/28f001bx-b 28f010 v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 gnd 290406 2 28f010 v cc we y nc a 14 a 13 a 8 a 9 a 11 oe y a 10 ce y dq 7 dq 6 dq 5 dq 4 dq 3 figure 2. dip pin configuration 28f010 a 11 a 9 a 8 a 13 a 14 nc we y v cc v pp a 16 a 15 a 12 a 7 a 6 a 5 a 4 290406 3 28f010 oe y a 10 ce y dq 7 dq 6 dq 5 dq 4 dq 3 gnd dq 2 dq 1 dq 0 a 0 a 1 a 2 a 3 figure 3. tsop lead configuration 3
28f001bx-t/28f001bx-b 290406 4 figure 4. plcc lead configuration applications the 28f001bx flash `boot block' memory augments the non-volatility, in-system electrical erasure and reprogrammability of intel's standard flash memory by offering four separately erasable blocks and inte- grating a state machine to control erase and pro- gram functions. the specialized blocking architec- ture and automated programming of the 28f001bx provide a full-function, non-volatile flash memory ideal for a wide range of applications, including pc boot/bios memory, minimum-chip embedded pro- gram memory and parametric data storage. the 28f001bx combines the safety of a hardware-pro- tected 8-kbyte boot block with the flexibility of three separately reprogrammable blocks (two 4-kbyte pa- rameter blocks and one 112-kbyte code block) into one versatile, cost-effective flash memory. addition- ally, reprogramming one block does not affect code stored in another block, ensuring data integrity. the flexibility of flash memory reduces costs throughout the life cycle of a design. during the early stages of a system's life, flash memory reduces pro- totype development and testing time, allowing the system designer to modify in-system software elec- trically versus manual removal of components. dur- ing production, flash memory provides flexible firm- ware for just-in-time configuration, reducing system inventory and eliminating unnecessary handling and less reliable socketed connections. late in the life cycle, when software updates or code ``bugs'' are often unpredictable and costly, flash memory reduc- es update costs by allowing the manufacturers to send floppy updates versus a technician. alterna- tively, remote updates over a communication link are possible at speeds up to 9600 baud due to flash memory's fast programming time. 4
28f001bx-t/28f001bx-b reprogrammable environments, such as the per- sonal computer, are ideal applications for the 28f001bx. the internal state machine provides sram-like timings for program and erasure, using the command and status registers. the blocking scheme allows bios update in the main and param- eter blocks, while still providing recovery code in the boot block in the unlikely event a power failure oc- curs during an update, or where bios code is cor- rupted. parameter blocks also provide convenient configuration storage, backing up sram and battery configurations. eisa systems, for example, can store hardware configurations in a flash parameter block, reducing system sram. laptop bioss are becoming increasingly complex with the addition of power management software and extended system setup screens. bios code complexity increases the potential for code updates after the sale, but the compactness of laptop de- signs makes hardware updates very costly. boot block flash memory provides an inexpensive update solution for laptops, while reducing laptop obsoles- cence. for portable pcs and hand-held equipment, the deep powerdown mode dramatically lowers sys- tem power requirements during periods of slow op- eration or sleep modes. the 28f001bx gives the embedded system design- er several desired features. the internal state ma- chine reduces the size of external code dedicated to the erase and program algorithms, as well as freeing the microcontroller or microprocessor to respond to other system requests during program and erasure. the four blocks allow logical segmentation of the entire embedded software: the 8-kbyte block for the boot code, the 112-kbyte block for the main pro- gram code and the two 4-kbyte blocks for updatable parametric data storage, diagnostic messages and data, or extensions of either the boot code or pro- gram code. the boot block is hardware protected against unauthorized write or erase of its vital code in the field. further, the powerdown mode also locks out erase or write operations, providing absolute data protection during system powerup or power loss. this hardware protection provides obvious ad- vantages for safety related applications such as transportation, military, and medical. the 28f001bx is well suited for minimum-chip embedded applica- tions ranging from communications to automotive. 290406 5 figure 5. 28f001bx-t in a 80c188 system 290406 6 figure 6. 28f001bx-b in a 80c51 system 5
28f001bx-t/28f001bx-b principles of operation the 28f001bx introduces on-chip write automation to manage write and erase functions. the write state machine allows for 100% ttl-level control inputs, fixed power supplies during erasure and program- ming, minimal processor overhead with ram-like write timings, and maximum eprom compatiblity. after initial device powerup, or after return from deep powerdown mode (see bus operations), the 28f001bx functions as a read-only memory. manip- ulation of external memory-control pins yield stan- dard eprom read, standby, output disable or intelli- gent identifier operations. both status register and intelligent identifiers can be accessed through the command register when v pp e v ppl . this same subset of operations is also available when high voltage is applied to the v pp pin. in addi- tion, high voltage on v pp enables successful erasure and programming of the device. all functions associ- ated with altering memory contentseprogram, erase, status, and int e ligent identifiereare accessed via the command register and verified through the status register. commands are written using standard microproces- sor write timings. register contents serve as input to the wsm, which controls the erase and program- ming circuitry. write cycles also internally latch ad- dresses and data needed for programming or erase operations. with the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output program and erase status for verifi- cation. interface software to initiate and poll progress of in- ternal program and erase can be stored in any of the 28f001bx blocks. this code is copied to, and exe- cuted from, system ram during actual flash memory update. after successful completion of program and/or erase, code execution out of the 28f001bx is again possible via the read array command. erase suspend/resume capability allows system software to suspend block erase and read data/exe- cute code from any other block. command register and write automation an on-chip state machine controls block erase and byte program, freeing the system processor for other tasks. after receiving the erase setup and erase confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the status register. programming is similarly controlled, after destination address and expected data are supplied. the program algorithm of past in- tel flash memories is now regulated by the state machine, including program pulse repetition where required and internal verification and margining of data. data protection depending on the application, the system designer may choose to make the v pp power supply switcha- ble (available only when memory updates are re- quired) or hardwired to v pph . when v pp e v ppl , memory contents cannot be altered. the 28f001bx command register architecture provides protection from unwanted program or erase operations even when high voltage is applied to v pp . additionally, all functions are disabled whenever v cc is below the write lockout voltage v lko , or when rp y is at v il . the 28f001bx accommodates either design prac- tice and encourages optimization of the processor- memory interface. the two-step program/erase write sequence to the command register provides additional software write protection. 1ffff 8-kbyte boot block 1dfff 1e000 4-kbyte parameter block 1cfff 1d000 4-kbyte parameter block 1bfff 1c000 112-kbyte main block 00000 figure 7. 28f001bx-t memory map 1ffff 112-kbyte main block 03fff 04000 4-kbyte parameter block 02fff 03000 4-kbyte parameter block 01fff 02000 8-kbyte boot block 00000 figure 8. 28f001bx-b memory map 6
28f001bx-t/28f001bx-b bus operation flash memory reads, erases and writes in-system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. read the 28f001bx has three read modes. the memory can be read from any of its blocks, and information can be read from the intelligent identifier or the status register. v pp can be at either v ppl or v pph . the first task is to write the appropriate read mode command to the command register (array, intelli- gent identifier, or status register). the 28f001bx automatically resets to read array mode upon initial device powerup or after exit from deep powerdown. the 28f001bx has four control pins, two of which must be logically active to obtain data at the outputs. chip enable (ce y ) is the device selection control, and when active enables the selected memory de- vice. output enable (oe y ) is the data input/output (dq 0 dq 7 ) direction control, and when active drives data from the selected memory onto the i/o bus. rp y and we y must also be at v ih . figure 12 illustrates read bus cycle waveforms. output disable with oe y at a logic-high level (v ih ), the device out- puts are disabled. output pins (dq 0 dq 7 ) are placed in a high-impedance state. standby ce y at a logic-high level (v ih ) places the 28f001bx in standby mode. standby operation disables much of the 28f001bx's circuitry and substantially reduc- es device power consumption. the outputs (dq 0 dq 7 ) are placed in a high-impedance state indepen- dent of the status of oe y . if the 28f001bx is dese- lected during erase or program, the device will continue functioning and consuming normal active power until the operation is completed. deep power-down the 28f001bx offers a 0.25 m wv cc power-down feature, entered when rp y is at v il . during read modes, rp y low deselects the memory, places out- put drivers in a high-impedance state and turns off all internal circuits. the 28f001bx requires time t phqv (see ac characteristics-read only opera- tions) after return from power-down until initial mem- ory access outputs are valid. after this wakeup inter- val, normal operation is restored. the command register is reset to read array, and the status reg- ister is cleared to value 80h, upon return to normal operation. during erase or program modes, rp y low will abort either operation. memory contents of the block be- ing altered are no longer valid as the data will be partially programmed or erased. time t phwl after rp y goes to logic-high (v ih ) is required before an- other command can be written. table 2. 28f001bx bus operations mode notes rp y ce y oe y we y a 9 a 0 v pp dq 07 read 1, 2, 3 v ih v il v il v ih xx x d out output disable 2 v ih v il v ih v ih x x x high z standby 2 v ih v ih x x x x x high z deep power down 2 v il x x x x x x high z intelligent identifier (mfr) 2, 3, 4 v ih v il v il v ih v id v il x 89h intelligent identifier (device) 2, 3, 4, 5 v ih v il v il v ih v id v ih x 94h, 95h write 2, 6, 7, 8 v ih v il v ih v il xx x d in notes: 1. refer to dc characteristics. when v pp e v ppl , memory contents can be read but not programmed or erased. 2. x can be v il or v ih for control pins and addresses, and v ppl or v pph for v pp . 3. see dc characteristics for v ppl ,v pph ,v hh and v id voltages. 4. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 3. a 1 a 8 , a 10 a 16 e v il . 5. device id e 94h for the 28f001bx-t and 95h for the 28f001bx-b. 6. command writes involving block erase or byte program are successfully executed only when v pp e v pph . 7. refer to table 3 for valid d in during a write operation. 8. program or erase the boot block by holding rp y at v hh or toggling oe y to v hh . see ac waveforms for program/erase operations. 7
28f001bx-t/28f001bx-b the use of rp y during system reset is important with automated write/erase devices. when the sys- tem comes out of reset it expects to read from the flash memory. automated flash memories provide status information when accessed during write/ erase modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization would not occur because the flash memory would be providing the status information instead of array data. intel's flash memories allow proper cpu initialization fol- lowing a system reset through the use of the rp y input. in this application rp y is controlled by the same reset y signal that resets the system cpu. intelligent identifier operation the intelligent identifier operation outputs the manu- facturer code, 89h; and the device code, 94h for the 28f001bx-t and 95h for the 28f001bx-b. pro- gramming equipment or the system cpu can then automatically match the device with its proper erase and programming algorithms. programming equipment ce y and oe y at a logic low level (v il ), with a 9 at high voltage v id (see dc characteristics) activates this operation. data read from locations 00000h and 00001h represent the manufacturer's code and the device code respectively. in-system programming the manufacturer- and device-codes can also be read via the command register. following a write of 90h to the command register, a read from address location 00000h outputs the manufacturer code (89h). a read from address 00001h outputs the de- vice code (94h for the 28f001bx-t and 95h for the 28f001bx-b). it is not necessary to have high volt- age applied to v pp to read the intelligent identifiers from the command register. write writes to the command register allow read of de- vice data and intelligent identifiers. they also con- trol inspection and clearing of the status register. additionally, when v pp e v pph , the command reg- ister controls device erasure and programming. the contents of the register serve as input to the internal state machine. the command register itself does not occupy an addressable memory location. the register is a latch used to store the command and address and data information needed to execute the command. erase setup and erase confirm commands require both appropriate command data and an address within the block to be erased. the program setup com- mand requires both appropriate command data and the address of the location to be programmed, while the program command consists of the data to be written and the address of the location to be pro- grammed. the command register is written by bringing we y to a logic-low level (v il ) while ce y is low. address- es and data are latched on the rising edge of we y . standard microprocessor write timings are used. refer to ac write characteristics and the ac wave- form for write operations, figure 13, for specific tim- ing parameters. command definitions when v ppl is applied to the v pp pin, read opera- tions from the status register, intelligent identifiers, or array blocks are enabled. placing v pph on v pp enables successful program and erase operations as well. device operations are selected by writing specific commands into the command register. table 3 de- fines these 28f001bx commands. read array command upon initial device powerup and after exit from deep-powerdown mode, the 28f001bx defaults to read array mode. this operation is also initiated by writing ffh into the command register. microproc- essor read cycles retrieve array data. the device re- mains enabled for reads until the command regis- ter contents are altered. once the internal write state machine has started an erase or program op- eration, the device will not recognize the read array command, until the wsm has completed its opera- tion. the read array command is functional when v pp e v ppl or v pph . intelligent identifier command for in-system programming the 28f001bx contains an intelligent identifier op- eration to supplement traditional prom-program- ming methodology. the operation is initiated by writ- ing 90h into the command register. following the command write, a read cycle from address 00000h retrieves the manufacturer code of 89h. a read cy- cle from address 00001h returns the device code of 94h (28f001bx-t) or 95h (28f001bx-b). to termi- nate the operation, it is necessary to write another valid command into the register. like the read array command, the intelligent identifier command is func- tional when v pp e v ppl or v pph . 8
28f001bx-t/28f001bx-b table 3. 28f001bx command definitions command cycles req'd bus notes first bus cycle second bus cycle operation address data operation address data read array/reset 1 1 write x ffh intelligent identifier 3 2, 3, 4 write x 90h read ia iid read status register 2 3 write x 70h read x srd clear status register 1 write x 50h erase setup/erase confirm 2 2 write ba 20h write ba d0h erase suspend/erase resume 2 write x b0h write x d0h program setup/program 2 2, 3 write pa 40h write pa pd notes: 1. bus operations are defined in table 2. 2. ia e identifier address: 00h for manufacturer code, 01h for device code. ba e address within the block being erased. pa e address of memory location to be programmed. 3. srd e data read from status register. see table 4 for a description of the status register bits. pd e data to be programmed at location pa. data is latched on the rising edge of we y . iid e data read from intelligent identifiers. 4. following the intelligent identifier command, two read operations access manufacture and device codes. 5. commands other than those shown above are reserved by intel for future device implementations and should not be used. read status register command the 28f001bx contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status register command (70h) to the command register. after writing this command, all subsequent read opera- tions output data from the status register, until an- other valid command is written to the command register. the contents of the status register are latched on the falling edge of oe y or ce y , which- ever occurs last in the read cycle. oe y or ce y must be toggled to v ih before further reads to up- date the status register latch. the read status register command functions when v pp e v ppl or v pph . clear status register command the erase status and program status bits are set to ``1'' by the write state machine and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 4). by allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). the status register may then be polled to determine if an error occurred during that series. this adds flexibility to the way the device may be used. additionally, the v pp status bit (sr.3), when set to ``1'', must be reset by system software before fur- ther byte programs or block erases are attempted. to clear the status register, the clear status regis- ter command (50h) is written to the command reg- ister. the clear status register command is func- tional when v pp e v ppl or v pph . 9
28f001bx-t/28f001bx-b table 4. 28f001bx status register definitions wsms ess es ps vpps r r r 76543210 sr.7 e write state machine status 1 e ready 0 e busy sr.6 e erase suspend status 1 e erase suspended 0 e erase in progress/completed sr.5 e erase status 1 e error in block erasure 0 e successful block erase sr.4 e program status 1 e error in byte program 0 e successful byte program sr.3 e v pp status 1 e v pp low detect; operation abort 0 e v pp ok sr.2 sr.0 e reserved for future enhance- ments these bits are reserved for future use and should be masked out when polling the status register. notes: the write state machine status bit must first be checked to determine program or erase completion, before the program or erase status bits are checked for success. if the program and erase status bits are set to ``1s'' dur- ing an erase attempt, an improper command sequence was entered. attempt the operation again. if v pp low status is detected, the status register must be cleared before another program or erase operation is at- tempted. the v pp status bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm in- terrogates the v pp level only after the program or erase command sequences have been entered and informs the system if v pp has not been switched on. the v pp status bit is not guaranteed to report accurate feedback be- tween v ppl and v pph . erase setup/erase confirm commands erase is executed one block at a time, initiated by a two-cycle command sequence. an erase setup command (20h) is first written to the command register, followed by the erase confirm command (d0h). these commands require both appropriate command data and an address within the block to be erased. block preconditioning, erase and verify are all handled internally by the write state machine, invisible to the system. after receiving the two-com- mand erase sequence, the 28f001bx automatically outputs status register data when read (see figure 10; block erase flowchart). the cpu can detect the completion of the erase event by checking the wsm status bit of the status register (sr.7). when the status register indicates that erase is complete, the erase status bit should be checked. if erase error is detected, the status register should be cleared. the command register remains in read status register mode until further commands are is- sued to it. this two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. also, block erasure can only occur when v pp e v pph . in the absence of this high volt- age, memory contents are protected against era- sure. if block erase is attempted while v pp e v ppl , the v pp status bit will be set to ``1''. erase attempts while v ppl k v pp k v pph produce spurious results and should not be attempted. erase suspend/erase resume commands the erase suspend command allows erase se- quence interruption in order to read data from anoth- er block of memory. once the erase sequence is started, writing the erase suspend command (b0h) to the command register requests that the wsm suspend the erase sequence at a predetermined point in the erase algorithm. the 28f001bx contin- ues to output status register data when read, after the erase suspend command is written to it. polling the wsm status and erase suspend status bits will determine when the erase operation has been sus- pended (both will be set to ``1s''). at this point, a read array command can be written to the command register to read data from blocks other than that which is suspended . the only oth- er valid commands at this time are read status reg- ister (70h) and erase resume (d0h), at which time the wsm will continue with the erase sequence. the erase suspend status and wsm status bits of the status register will be cleared. after the erase re- sume command is written to it, the 28f001bx auto- matically outputs status register data when read (see figure 11; erase suspend/resume flowchart). 10
28f001bx-t/28f001bx-b program setup/program commands programming is executed by a two-write sequence. the program setup command (40h) is written to the command register, followed by a second write specifying the address and data (latched on the ris- ing edge of we y ) to be programmed. the wsm then takes over, controlling the program and verify algorithms internally. after the two-command pro- gram sequence is written to it, the 28f001bx auto- matically outputs status register data when read (see figure 9; byte program flowchart). the cpu can detect the completion of the program event by analyzing the wsm status bit of the status register. only the read status register command is valid while programming is active. when the status register indicates that program- ming is complete, the program status bit should be checked. if program error is detected, the status register should be cleared. the internal wsm verify only detects errors for ``1s'' that do not successfully program to ``0s''. the command register remains in read status register mode until further commands are issued to it. if byte program is attempted while v pp e v ppl , the v pp status bit will be set to ``1''. program attempts while v ppl k v pp k v pph pro- duce spurious results and should not be attempted. extended erase/program cycling eeprom cycling failures have always concerned users. the high electrical field required by thin oxide eeproms for tunneling can literally tear apart the oxide at defect regions. to combat this, some sup- pliers have implemented redundancy schemes, re- ducing cycling failures to insignificant levels. howev- er, redundancy requires that cell size be doubled; an expensive solution. intel has designed extended cycling capability into its etox flash memory technology. resulting im- provements in cycling reliability come without in- creasing memory cell size or complexity. first, an advanced tunnel oxide increases the charge carry- ing ability ten-fold. second, the oxide area per cell subjected to the tunneling electrical field is one- tenth that of common eeproms, minimizing the probability of oxide defects in the region. finally, the peak electric field during erasure is approximately 2 mv/cm lower than eeprom. the lower electric field greatly reduces oxide stress and the probability of failure. the 28f001bx-b and 28f001bx-t are capable of 100,000 program/erase cycles on each parameter block, main block and boot block. on-chip programming algorithm the 28f001bx integrates the quick pulse program- ming algorithm of prior intel flash memory devices on-chip, using the command register, status regis- ter and write state machine (wsm). on-chip inte- gration dramatically simplifies system software and provides processor-like interface timings to the command and status registers. wsm operation, in- ternal program verify and v pp high voltage presence are monitored and reported via appropriate status register bits. figure 9 shows a system software flowchart for device programming. the entire se- quence is performed with v pp at v pph . program abort occurs when rp y transitions to v il ,orv pp drops to v ppl . although the wsm is halted, byte data is partially programmed at the location where programming was aborted. block erasure or a re- peat of byte programming will initialize this data to a known value. on-chip erase algorithm as above, the quick erase algorithm of prior intel flash memory devices is now implemented internal- ly, including all preconditioning of block data. wsm operation, erase success and v pp high voltage pres- ence are monitored and reported through the status register. additionally, if a command other than erase confirm is written to the device after erase setup has been written, both the erase status and program status bits will be set to ``1''. when issuing the erase setup and erase confirm commands, they should be written to an address within the address range of the block to be erased. figure 10 shows a system software flowchart for block erase. erase typically takes 1 4 seconds per block. the erase suspend/erase resume command sequence allows interrupt of this erase operation to read data from a block other than that in which erase is being performed . a system software flowchart is shown in figure 11. the entire sequence is performed with v pp at v pph . abort occurs when rp y transitions to v il or v pp falls to v ppl , while erase is in progress. block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. 11
28f001bx-t/28f001bx-b boot block program and erase the boot block is intended to contain secure code which will minimally bring up a system and control programming and erase of other blocks of the de- vice, if needed. therefore, additional ``lockout'' pro- tection is provided to guarantee data integrity. boot block program and erase operations are enabled through high voltage v hh on either rp y or oe y , and the normal program and erase command se- quences are used. reference the ac waveforms for program/erase. if boot block program or erase is attempted while rp y is at v ih , either the program status or erase status bit will be set to ``1'', reflective of the opera- tion being attempted and indicating boot block lock. program/erase attempts while v ih k rp y k v hh produce spurious results and should not be attempt- ed. in-system operation for on-board programming, the rp y pin is the most convenient means of altering the boot block. before issuing program or erase confirms commands, rp y must transition to v hh . hold rp y at this high volt- age throughout the program or erase interval (until after status register confirm of successful comple- tion). at this time, it can return to v ih or v il . 290406 7 bus command comments operation write program data e 40h setup address e byte to be programmed write program data to be programmed address e byte to be programmed read status register data. toggle oe y or ce y to update status register standby check sr.7 1 e ready, 0 e busy repeat for subsequent bytes. full status check can be done after each byte or after a sequence of bytes. write ffh after the last byte programming operation to reset the device to read array mode. bus command comments operation standby check sr.3 1 e v pp low detect standby check sr.4 1 e byte program error sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.4 is only cleared by the clear status register command, in cases where multiple bytes are programmed before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 9. 28f001bx byte programming flowchart 12
28f001bx-t/28f001bx-b 290406 8 bus command comments operation write erase data e 20h setup address e within block to be erased write erase data e d0h address e within block to be erased read status register data. toggle oe y or ce y to update status register standby check sr.7 1 e ready, 0 e busy repeat for subsequent blocks. full status check can be done after each block or after a sequence of blocks. write ffh after the last block erase operation to reset the device to read array mode. bus command comments operation standby check sr.3 1 e v pp low detect standby check sr.4, 5 both 1 e command sequence error standby check sr.5 1 e block erase error sr.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.5 is only cleared by the clear status register command, in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 10. 28f001bx block erase flowchart 13
28f001bx-t/28f001bx-b 290406 9 bus command comments operation write erase data e b0h suspend write erase data e 70h status register standby/ read status register read check sr.7 1 e ready, 0 e busy toggle oe y or ce y to update status register standby check sr.6 1 e suspended write read array data e ffh read read array data from block other than that being erased. write erase resume data e d0h figure 11. 28f001bx erase suspend/resume flowchart programming equipment for prom programming equipment that cannot bring rp y to high voltage, oe y provides an alter- nate boot block access mechanism. oe y must tran- sition to v hh a minimum of 480 ns before the initial program/erase setup command and held at v hh at least 480 ns after program or erase confirm com- mands are issued to the device. after this interval, oe y can return to normal ttl levels. design considerations three-line output control flash memories are often used in larger memory ar- rays. intel provides three control inputs to accommo- date multiple memory connections. three-line con- trol provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur to efficiently use these control inputs, an address decoder should enable ce y , while oe y should be connected to all memory devices and the system's read y control line. this assures that only selected memory devices have active outputs while deselect- ed memory devices are in standby mode. rp y should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 14
28f001bx-t/28f001bx-b power supply decoupling flash memory power switching characteristics re- quire careful device coupling. system designers are interested in 3 supply current issues; standby current levels (i sb ), active current levels (i cc ) and transient peaks producted by falling and rising edges of ce y . transient current magnitudes depend on the device outputs' capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 m f ceramic capacitor connected between its v cc and gnd, and between its v pp and gnd. these high frequency, low inherent-induc- tance capacitors should be placed as close as pos- sible to the device. additionally, for every 8 devices, a 4.7 m f electrolytic capacitor should be placed at the array's power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductances. v pp trace on printed circuit boards programming flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the v pp power sup- ply trace. the v pp pin supplies the memory cell cur- rent for programming. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will de- crease v pp voltage spikes and overshoots. v cc ,v pp ,rp y transitions and the command/status registers programming and erase completion are not guaran- teed if v pp drops below v pph . if the v pp status bit of the status register (sr.3) is set to ``1'', a clear status register command must be issued before further program/erase attempts are allowed by the wsm. otherwise, the program (sr.4) or erase (sr.5) status bits of the status register will be set to ``1'' if error is detected. rp y transitions to v il during program and erase also abort the operations. data is partially altered in either case, and the com- mand sequence must be repeated after normal op- eration is restored. device poweroff, or rp y tran- sitions to v il , clear the status register to initial val- ue 80h. the command register latches commands as is- sued by system software and is not altered by v pp or ce y transitions or wsm actions. its state upon powerup, after exit from deep-powerdown or after v cc transitions below v lko , is ffh, or read array mode. after program or erase is complete, even after v pp transitions down to v ppl , the command register must be reset to read array mode via the read array command if access to the memory array is desired. power up/down protection the 28f001bx is designed to offer protection against accidental erasure or programming during power transitions. upon power-up, the 28f001bx is indifferent as to which power supply, v pp or v cc , powers up first. power supply sequencing is not re- quired. internal circuitry in the 28f001bx ensures that the command register is reset to read array mode on power up. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we y and ce y must be low for a command write, driving either to v ih will inhibit writes. the command register architecture provides an added level of protection since alteration of mem- ory contents only occurs after successful completion of the two-step command sequences. finally, the device is disabled, until rp y is brought to v ih , regardless of the state of its control inputs. this provides an additional level of protection. 28f001bx power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash nonvolatility increases us- able battery life because the 28f001bx does not consume any power to retain code or data when the system is off. in addition, the 28f001bx's deep-powerdown mode ensures extremely low power dissipation even when system power is applied. for example, laptop and other pc applications, after copying bios to dram, can lower rp y to v il , producing negligible power consumption. if access to the boot code is again needed, as in case of a system reset y , the part can again be accessed, following the t phav wakeup cycle required after rp y is first raised back to v ih . the first address presented to the device while in powerdown requires time t phav , after rp y tran- sitions high, before outputs are valid. further ac- cesses follow normal timing. see ac characteris- ticseread-only operations and figure 12 for more information. 15
28f001bx-t/28f001bx-b absolute maximum ratings * operating temperature during read 0 cto70 c (1) during erase/program 0 cto70 c (1) operating temperature during read b 40 cto a 85 c (2) during erase/program b 40 cto a 85 c (2) temperature under bias b 10 cto80 c (1) temperature under bias b 20 cto a 90 c (2) storage temperature b 65 cto125 c voltage on any pin (except a 9 ,rp y ,oe y ,v cc and v pp ) with respect to gnd b 2.0v to 7.0v (3) voltage on a 9 ,rp y , and oe y with respect to gnd b 2.0v to 13.5v (3, 4) v pp program voltage with respect to gnd during erase/program b 2.0v to 14.0v (3, 4) v cc supply voltage with respect to gnd b 2.0v to 7.0v (3) output short circuit current100 ma (5) notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol parameter min max unit t a operating temperature (1) 070 c t a operating temperature (2) b 40 85 c v cc supply voltage 4.50 5.50 v notes: 1. operating temperature is for commercial product defined by this specification. 2. operating temperature is for extended temperature product defined by this specification. 3. minimum dc voltage is b 0.5v on input/output pins. during transitions, this level may undershoot to b 2.0v for periods k 20 ns. maximum dc voltage on input/output pins is v cc a 0.5v which, during transitions, may overshoot to v cc a 2.0v for periods k 20 ns. 4. maximum dc voltage on a 9 or v pp may overshoot to a 14.0v for periods k 20 ns. 5. output shorted for no more than one second. no more than one output shorted at a time. dc characteristics v cc e 5.0v g 10%, t a e 0 cto a 70 c symbol parameter notes min typ max unit test conditions i il input load current 1 g 1.0 m av cc e v cc max v in e v cc or gnd i lo output leakage current 1 g 10 m av cc e v cc max v out e v cc or gnd i ccs v cc standby current 1.2 2.0 ma v cc e v cc max ce y e rp y e v ih 30 100 m av cc e v cc max ce y e rp y e v cc g 0.2v i ccd v cc deep power-down current 1 0.05 1.0 m arp y e gnd g 0.2v 16
28f001bx-t/28f001bx-b dc characteristics (continued) v cc e 5.0v g 10%, t a e 0 cto a 70 c symbol parameter notes min typ max unit test conditions i ccr v cc read current 1 13 30 ma v cc e v cc max, ce y e v il f e 8 mhz, i out e 0ma i ccp v cc programming current 1 5 20 ma programming in progress i cce v cc erase current 1 6 20 ma erase in progress i cces v cc erase suspend current 1, 2 5 10 ma erase suspended ce y e v ih i pps v pp standby current 1 g 1 g 10 m av pp s v cc 90 200 m av pp l v cc i ppd v pp deep power-down current 1 0.80 1.0 m arp y e gnd g 0.2v i ppp v pp programming current 1 6 30 ma v pp e v pph programming in progress i ppe v pp erase current 1 6 30 ma v pp e v pph erase in progress i ppes v pp erase suspend current 1 90 300 m av pp e v pph erase suspended i id a 9 intelligent identifier current 1 90 500 m aa 9 e v id v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v ol output low voltage 0.45 v v cc e v cc min i ol e 5.8 ma v oh output high voltage 2.4 v v cc e v cc min i oh e 2.5 ma v id a 9 intelligent identifier voltage 11.5 13.0 v v ppl v pp during normal operations 3 0.0 6.5 v v pph v pp during prog/erase operations 11.4 12.0 12.6 v v lko v cc erase/write lock voltage 2.5 v v hh rp y ,oe y unlock voltage 11.4 12.6 v boot block prog/erase notes: 1. all currents are in rms unless otherwise noted. typical values at v cc e 5.0v, v pp e 12.0v, t a e 25 c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device deselected. if the 28f001bx is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. erase/programs are inhibited when v pp e v ppl and not guaranteed in the range between v pph and v ppl . 17
28f001bx-t/28f001bx-b dc characteristics v cc e 5.0v g 10%, t a eb 40 cto a 85 c symbol parameter notes min typ max unit test conditions i il input load current 1 g 1.0 m av cc e v cc max v in e v cc or gnd i lo output leakage current 1 g 10 m av cc e v cc max v out e v cc or gnd i ccs v cc standby current 1.2 2.0 ma v cc e v cc max ce y e rp y e v ih 30 150 m av cc e v cc max ce y e rp y e v cc g 0.2v i ccd v cc deep power-down current 1 0.05 2.0 m arp y e gnd g 0.2v i ccr v cc read current 1 13 35 ma v cc e v cc max, ce y e v il f e 8 mhz, i out e 0ma i ccp v cc programming current 1 5 20 ma programming in progress i cce v cc erase current 1 6 20 ma erase in progress i cces v cc erase suspend current 1, 2 5 10 ma erase suspended ce y e v ih i pps v pp standby current 1 g 1 g 15 m av pp s v cc 90 400 m av pp l v cc i ppd v pp deep power-down current 1 0.80 1.0 m arp y e gnd g 0.2v i ppp v pp programming current 1 6 30 m av pp e v pph programming in progress i ppe v pp erase current 1 6 30 ma v pp e v pph erase in progress i ppes v pp erase suspend current 1 90 400 m av pp e v pph erase suspended i id a 9 intelligent identifier current 1 90 500 m aa 9 e v id v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v ol output low voltage 0.45 v v cc e v cc min i ol e 5.8 ma v oh1 output high voltage (ttl) 2.4 v v cc e v cc min i oh e 2.5 ma v oh2 output high voltage (cmos) 0.85 v cc vv cc e v cc min i oh eb 2.5 m a v cc b 0.4 v cc e v cc min i oh eb 100 m a v id a 9 intelligent identifier voltage 11.5 13.0 v v ppl v pp during normal operations 3 0.0 6.5 v v pph v pp during prog/erase operations 11.4 12.0 12.6 v v lko v cc erase/write lock voltage 2.5 v v hh rp y ,oe y unlock voltage 11.4 12.6 v boot block prog/erase 18
28f001bx-t/28f001bx-b notes: 1. all currents are in rms unless otherwise noted. typical values at v cc e 5.0v, v pp e 12.0v, t a e 25 c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device deselected. if the 28f001bx is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. erase/programs are inhibited when v pp e v ppl and not guaranteed in the range between v pph and v ppl . capacitance (1) t a e 25 c, f e 1 mhz symbol parameter max unit conditions c in input capacitance 8 pf v in e 0v c out output capacitance 12 pf v out e 0v note: 1. sampled, not 100% tested. ac input/output reference waveform 290406 10 a.c. test inputs are driven at v oh (2.4 v ttl ) for a logic ``1'' and v ol (0.45 v ttl ) for a logic ``0''. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) k 10 ns. standard test configuration ac testing load circuit 290406 11 c l e 100 pf c l includes jig capacitance r l e 3.3 k x high speed test configuration ac testing load circuit 290406 23 c l e 30 pf c l includes jig capacitance r l e 3.3 k x 19
28f001bx-t/28f001bx-b ac characteristicseread-only operations (1) symbol parameter notes 28f001bx-70 28f001bx-90 units v cc e 5v v cc e 5v v cc e 5v g 5% g 10% g 10% 30 pf 100 pf 100 pf min max min max min max t avav t rc read cycle time 70 75 90 ns t avqv t acc address to output delay 70 75 90 ns t elqv t ce ce y to output delay 2 70 75 90 ns t phqv t pwh rp y to output delay 600 600 600 ns t glqv t oe oe y to output delay 2 27 30 35 ns t elqx t lz ce y to output in low z 3 0 0 0 ns t ehqz t hz ce y to output in high z 3 55 55 35 ns t glqx t olz oe y to output in low z 3 0 0 0 ns t ghqz t df oe y to output in high z 3 30 30 30 ns t oh output hold from 3 0 0 0 ns address ce y ,oroe y change, whichever occurs first notes: 1. see ac input/output reference waveform for timing measurements. 2. oe y may be delayed up to t ce t oe after the falling edge of ce y without impact on t ce . 3. sampled, but not 100% tested. 4. see high speed test configuration. 5. see standard test configuration. 20
28f001bx-t/28f001bx-b ac characteristicseread-only operations (1) e28f001bx-150 unit e28f001bx-120 te28f001bx-150 versions (2) v cc g 10% n28f001bx-120 n28f001bx-150 p28f001bx-120 tn28f001bx-150 p28f001bx-150 symbol parameter notes min max min max t avav t rc read cycle time 120 150 ns t avqv t acc address to output delay 120 150 ns t elqv t ce ce y to output delay 3 120 150 ns t phqv t pwh rp y high to output delay 600 600 ns t glqv t oe oe y to output delay 3 50 55 ns t elqx t lz ce y to output low z 4 0 0 ns t ehqz t hz ce y high to output high z 4 55 55 ns t glqx t olz oe y to output low z 4 0 0 ns t ghqz t df oe y high to output high z 4 30 30 ns t oh output hold from 4 0 0 ns addresses, ce y or oe y change, whichever is first notes: 1. see ac input/output reference waveform for timing measurements. 2. model number prefixes: e e tsop (standard pinout), n e plcc, p e pdip, t e extended temperature. refer to standard test configuration. 3. oe y may be delayed up to t ce t oe after the falling edge of ce y without impact on t ce . 4. sampled, not 100% tested. 21
28f001bx-t/28f001bx-b figure 12. ac waveform for read operations 290406 12 22
28f001bx-t/28f001bx-b ac characteristicsewrite/erase/program operations (1, 9) symbol parameter notes 28f001bx-70 28f001bx-90 units v cc e 5v v cc e 5v v cc e 5v g 5% (10) g 10% (11) g 10% (11) 30 pf 100 pf 100 pf min max min max min max t avav t wc write cycle time 70 75 90 ns t phwl t ps rp y high recovery to we y 2 480 480 480 ns going low t elwl t cs ce y setup to we y going low 10 10 10 ns t wlwh t wp we y pulse width 35 40 40 ns t phhwh t phs rp y v hh setup to we y going 2 100 100 100 ns high t vpwh t vps v pp setup to we y going high 2 100 100 100 ns t avwh t as address setup to we y going 3 35 40 40 ns high t dvwh t ds data setup to we y going high 4 35 40 40 ns t whdx t dh data hold from we y high 10 10 10 ns t whax t ah address hold from we y high 10 10 10 ns t wheh t ch ce y hold from we y high 10 10 10 ns t whwl t wph we y pulse width high 35 35 35 ns t whqv1 duration of programming 5, 6, 7 15 15 15 m s operation t whqv2 duration of erase operation 5, 6, 7 1.3 1.3 1.3 sec (boot) t whqv3 duration of erase operation 5, 6, 7 1.3 1.3 1.3 sec (parameter) t whqv4 duration of erase operation 5, 6, 7 3.0 3.0 3.0 sec (main) t whgl write recovery before read 0 0 0 m s t qvvl t vph v pp hold from valid srd 2, 6 0 0 0 ns t qvph t phh rp y v hh hold from valid srd 2, 7 0 0 0 ns t phbr boot-block relock delay 2 100 100 100 ns notes: 1. read timing characteristics during erase and program operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in for byte programming or block erasure. 4. refer to table 3 for valid d in for byte programming or block erasure. 5. the on-chip write state machine incorporates all program and erase system functions and overhead of standard intel flash memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase verify (erasing). 6. program and erase durations are measured to completion (sr.7 e 1). v pp should be held at v pph until determination of program/erase success (sr.3/4/5 e 0). 7. for boot block programming and erasure, rp y should be held at v hh until determination of program/erase success (sr.3/4/5 e 0). 8. alternate boot block access method. 9. erase/program cycles on extended temperature products is 10,000 cycles. 10. see high speed test configuration. 11. see standard test configuration. 23
28f001bx-t/28f001bx-b ac characteristicsewrite/erase/program operations (1, 9) versions v cc g 10% (10) 28f001bx-120 28f001bx-150 unit symbol parameter notes min max min max t avav t wc write cycle time 120 150 ns t phwl t ps rp y high recovery to we y going low 2 480 480 ns t elwl t cs ce y setup to we y going low 10 10 ns t wlwh t wp we y pulse width 50 50 ns t phhwh t phs rp y v hh setup to we y going high 2 100 100 ns t vpwh t vps v pp setup to we y going high 2 100 100 ns t avwh t as address setup to we y going high 3 50 50 ns t dvwh t ds data setup to we y going high 4 50 50 ns t whdx t dh data hold from we y high 10 10 ns t whax t ah address hold from we y high 10 10 ns t wheh t ch ce y hold from we y high 10 10 ns t whwl t wph we y pulse width high 50 50 ns t whqv1 duration of programming operation 5, 6, 7 15 15 m s t whqv2 duration of erase operation (boot) 5, 6, 7 1.3 1.3 sec t whqv3 duration of erase operation (parameter) 5, 6, 7 1.3 1.3 sec t whqv4 duration of erase operation (main) 5, 6, 7 3.0 3.0 sec t whgl write recovery before read 0 0 m s t qvvl t vph v pp hold from valid srd 2, 6 0 0 ns t qvph t phh rp y v hh hold from valid srd 2, 7 0 0 ns t phbr boot-block relock delay 2 100 100 ns prom programmer specifications versions v cc g 10% 28f001bx-120 28f001bx-150 unit symbol parameter notes min max min max t ghhwl oe y v hh setup to we y going low 2, 8 480 480 ns t whgh oe y v hh hold from we y high 2, 8 480 480 ns notes: 1. read timing characteristics during erase and program operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in for byte programming or block erasure. 4. refer to table 3 for valid d in for byte programming or block erasure. 5. the on-chip write state machine incorporates all program and erase system functions and overhead of standard intel flash memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase verify (erasing). 6. program and erase durations are measured to completion (sr.7 e 1). v pp should be held at v pph until determination of program/erase success (sr.3/4/5 e 0). 7. for boot block programming and erasure, rp y should be held at v hh until determination of program/erase success (sr.3/4/5 e 0). 8. alternate boot block access method. 9. erase/program cycles on extended temperature products is 10,000 cycles. 10. see standard test configuration. 24
28f001bx-t/28f001bx-b erase and programming performance parameter notes 28f001bx-120 28f001bx-150 unit min typ (1) max min typ (1) max boot block erase time 2 2.10 14.9 2.10 14.9 sec boot block program time 2 0.15 0.52 0.15 0.52 sec parameter block erase time 2 2.10 14.6 2.10 14.6 sec parameter block program time 2 0.07 0.26 0.07 0.26 sec main block erase time 2 3.80 20.9 3.80 20.9 sec main block program time 2 2.10 7.34 2.10 7.34 sec chip erase time 2 10.10 65 10.10 65 sec chip program time 2 2.39 8.38 2.39 8.38 sec notes: 1. 25 c, 12.0 v pp . 2. excludes system-level overhead. 25
28f001bx-t/28f001bx-b 290406 19 figure 13. 28f001bx typical programming capability 290406 20 figure 14. 28f001bx typical programming time at 12v 290406 21 figure 15. 28f001bx typical erase capability 290406 22 figure 16. 28f001bx typical erase time at 12v 26
28f001bx-t/28f001bx-b figure 17. ac waveform for write operations 290406 13 27
28f001bx-t/28f001bx-b 290406 15 figure 18. alternate boot block access method using oe y 28
28f001bx-t/28f001bx-b ac characteristics for ce y -controlled writes (1) symbol parameter notes 28f001bx-70 28f001bx-90 units v cc e 5v v cc e 5v v cc e 5v g 5% (8) g 10% (9) g 10% (9) 30 pf 100 pf 100 pf min max min max min max t avav t wc write cycle time 70 75 90 ns t phel t ps rp y high recovery to ce y 2 480 480 480 ns going low t wlel t ws we y setup to ce y going low 0 0 0 ns t eleh t cp ce y pulse width 50 55 55 ns t phheh t phs rp y v hh setup to ce y going 2 100 100 100 ns high t vpeh t vps v pp setup to ce y going high 2 100 100 100 ns t aveh t as address setup to ce y going 3 35 40 40 ns high t dveh t ds data setup to ce y going high 4 35 40 40 ns t ehdx t dh data hold from ce y high 10 10 10 ns t ehax t ah address hold from ce y high 10 10 10 ns t ehwh t wh we y hold from ce y high 0 0 0 ns t ehel t eph ce y pulse width high 20 20 20 ns t ehqv1 duration of programming 5, 6 15 15 15 m s operation t ehqv2 duration of erase operation 5, 6 1.3 1.3 1.3 sec (boot) t ehqv3 duration of erase operation 5, 6 1.3 1.3 1.3 sec (parameter) t ehqv4 duration of erase operation 5, 6 3.0 3.0 3.0 sec (main) t ehgl write recovery before read 0 0 0 m s t qvvl t vph v pp hold from valid srd 2, 5 0 0 0 ns t qvph t phh rp y v hh hold from valid srd 2, 6 0 0 0 ns t phbr boot-block relock delay 2 100 100 100 ns notes: 1. chip-enable controlled writes: write operations are driven by the valid combination of ce y and we y . in systems where ce y defines the write pulse width (within a longer we y timing waveform), all set-up, hold and inactive we y times should be measured relative to the ce y waveform. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in for byte programming or block erasure. 4. refer to table 3 for valid d in for byte programming or block erasure. 5. program and erase durations are measured to completion (sr.7 e 1). v pp should be held at v pph until determination of program/erase success (sr.3/4/5 e 0). 6. for boot block programming and erasure, rp y should be held at v hh until determination of program/erase success (sr.3/4/5 e 0). 7. alternate boot block access method. 8. see high speed test configuration. 9. see standard text configuration. 29
28f001bx-t/28f001bx-b ac characteristics for ce y -controlled writes (1) versions v cc g 10% 28f001bx-120 28f001bx-150 unit symbol parameter notes min max min max t avav t wc write cycle time 120 150 ns t phel t ps rp y high recovery to ce y going low 2 480 480 ns t wlel t ws we y setup to ce y going low 0 0 ns t eleh t cp ce y pulse width 70 70 ns t phheh t phs rp y v hh setup to ce y going high 2 100 100 ns t vpeh t vps v pp setup to ce y going high 2 100 100 ns t aveh t as address setup to ce y going high 3 50 50 ns t dveh t ds data setup to ce y going high 4 50 50 ns t ehdx t dh data hold from ce y high 10 10 ns t ehax t ah address hold from ce y high 15 15 ns t ehwh t wh we y hold from ce y high 0 0 ns t ehel t eph ce y pulse width high 25 25 ns t ehqv1 duration of programming operation 5, 6 15 15 m s t ehqv2 duration of erase operation (boot) 5, 6 1.3 1.3 sec t ehqv3 duration of erase operation (parameter) 5, 6 1.3 1.3 sec t ehqv4 duration of erase operation (main) 5, 6 3.0 3.0 sec t ehgl write recovery before read 0 0 m s t qvvl t vph v pp hold from valid srd 2, 5 0 0 ns t qvph t phh rp y v hh hold from valid srd 2, 6 0 0 ns t phbr boot-block relock delay 2 100 100 ns prom programmer specifications versions v cc g 10% 28f001bx-120 28f001bx-150 unit symbol parameter notes min max min max t ghhel oe y v hh setup to ce y going low 2, 7 480 480 ns t ehgh oe y v hh hold from ce y high 2, 7 480 480 ns notes: 1. chip-enable controlled writes: write operations are driven by the valid combination of ce y and we y . in systems where ce y defines the write pulse width (within a longer we y timing waveform), all set-up, hold and inactive we y times should be measured relative to the ce y waveform. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in for byte programming or block erasure. 4. refer to table 3 for valid d in for byte programming or block erasure. 5. program and erase durations are measured to completion (sr.7 e 1). v pp should be held at v pph until determination of program/erase success (sr.3/4/5 e 0). 6. for boot block programming and erasure, rp y should be held at v hh until determination of program/erase success (sr.3/4/5 e 0). 7. alternate boot block access method. 30
28f001bx-t/28f001bx-b figure 19. alternate ac waveform for write operations 290406 16 31
28f001bx-t/28f001bx-b ordering information 290406 18 valid combinations: 32-lead tsop 32-lead plcc 32-pin pdip commercial e28f001bx-t70 n28f001bx-t70 p28f001bx-t70 e28f001bx-t90 n28f001bx-t90 p28f001bx-t90 e28f001bx-t120 n28f001bx-t120 p28f001bx-t120 e28f001bx-t150 n28f001bx-t150 P28F001BX-T150 e28f001bx-b70 n28f001bx-b70 p28f001bx-b70 e28f001bx-b90 n28f001bx-b90 p28f001bx-b90 e28f001bx-b120 n28f001bx-b120 p28f001bx-b120 e28f001bx-b150 n28f001bx-b150 p28f001bx-b150 extended te28f001bx-t90 tn28f001bx-t90 tp28f001bx-t90 te28f001bx-t150 tn28f001bx-t150 tp28f001bx-b90 te28f001bx-b90 tn28f001bx-b90 te28f001bx-b150 tn28f001bx-b150 additional information references order number document 292046 ap-316 ``using flash memory for in-system reprogrammable nonvolatile storage'' 292077 ap-341 ``designing an updateable bios using flash memory'' 292161 ap-608 ``implementing a plug and play bios using intel's boot block flash memory'' 292178 ap-623 ``multi-site layout planning using intel's boot block flash memory'' 294005 er-20 ``etox ii flash memory technology'' 32
28f001bx-t/28f001bx-b revision history number description -004 removed preliminary classification. latched address a 16 in figure 5. updated boot block program and erase section: ``if boot block program or erase is attempted while rp y is at v ih , either the program status or erase status bit will be set to ``1'', reflective of the operation being attempted and indicating boot block lock.'' updated figure 11, 28f001bx erase suspend/resume flowchart added dc characteristics typical current values combined v pp standby current and v pp read current into one v pp standby current spec with two test conditions (dc characteristics table) added maximum program/erase times to erase and programming performance table. added figures 13 16 added extended temperature proliferations -005 pwd changed to rp y for jedec standardization compatibility revised symbols, i.e.; ce ,oe , etc. to ce y ,oe y , etc. -006 added specifications for -90 and -70 product versions. added v oh cmos specification. -007 added reference to 28f001bn. 33

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